Switching Noise Board

Project Overview

This board was designed to show the impact of following best practices on switching noise when laying out a Printed Circuit Board (PCB). Two identical hex inverter circuits will be identical and use the SN74AC14N, a six-channel hex inverter Integrated Circuit (IC). The first circuit will be referred to as the “Good Circuit” and will follow best practices such as using a continuous return plane and placing decoupling capacitors near the integrated circuit (IC) power pin. The second, “Bad Circuit”, will not have a ground plane underneath and will position the decoupling capacitors far from the IC power pin. The switching noise reduction from using best practices shows up to a 75% drop in switching noise.

Figure 1: Initial sketch of the proposed design. The board is comprised of four major functional groups: power conditioning for 5 and 3.3 volts, the timer circuit, a good hex inverter circuit, and a bad hex inverter circuit. The hex inverter circuits each drive an array of LEDs. A series of test points will be attached to various pins on the hex inverter and one LED for both circuits to compare the noise on the reference plane and the power rail.

Figure 1 shows the proposed design for the PCB and builds on a previously designed timer circuit1. The inverters will be able to be powered by either the 5V external power or the 3.3V output from the Low Drop Out (LDO) voltage regulator. The output from the 555 timer, which operates at approximately a 50% duty cycle of 500Hz, will drive four of the inverters on each IC. The output from three of the inverters will drive Light Emitting Diodes (LEDs) while one will be used to trigger the scope for signal analysis. One of the remaining inverters on the IC will have its output driven high, and the final inverter will have its output driven low; these outputs will be referred to as quite high and quite low, respectively.

The acceptance criteria for this board on bring-up are as follows:

The power rails are stable at 3.3V and 5V.
The 555 timer output duty cycle is between 40% and 80%.
The 555 timer output duty cycle frequency is between 200 and 1,000Hz.
The appropriate LEDs illuminate when the 555 timer and power are toggled to the appropriate inverter circuit.
Quiet high, quiet low, inverter output and the current through one LED can be measured for both circuits.

Board Design Features

Figure 2 shows the final schematic for the design. This design uses the power conditioning and 555 timer circuit from the previously designed Timer Board1. Additional features include the LDO which provides 3.3V power and the the hex inverter ICs. Each functional group can be isolated from the rest of the circuit. Test Points are attached to the output of one inverter, quiet high, quiet low, and one LED for each inverter circuit. These will allow analysis of the switching noise performance for each circuit. The final layout and assembled board are shown in Figure 3 and Figure 4, respectively. The bad hex inverter circuit does not have a return plane underneath it, has its decoupling capacitor positioned far from the IC through an unnecessarily long trace, and has inverter outputs share return lines. These are all examples of bad practices which produce a significant amount of switching noise.

Bring-up was done incrementally and was uneventful. Both the 3.3V and 5V power rails were verified to produce stable power at their respective voltage. The 555 timer circuit was verified to have a frequency of 500Hz and a 65% duty cycle. The appropriate LEDs are illuminated when driven by the timer circuit and enabled. Additionally, a slight reduction in the LED brightness was noted when switching from 5V to 3.3V. One unexpected result was that when a hex circuit is disabled, but being driven by the timer circuit, the LEDs illuminate slightly. Future design considerations to avoid this are discussed in the lessons learned section.

Figure 2: The schematic for the Switching Noise Board design. The power conditioning circuit includes indicator LEDs for both 3.3V and 5V as well as the ability to turn off the 3.3V circuit and its decoupling capacitor. The hex inverters can be powered by either 3.3V or 5V from the power conditioning circuit and each circuit can be disconnected via their respective isolation switches. Additionally, the output from the 555 timer can be toggled between the two hex inverter circuits.

Figure 3: The final board layout showing the reference plane on the back of the board in blue, the top layer coper traces in red, the bottom layer coper races in black, and the text on the top of the silk screen in yellow.

Figure 4: The fully assembled board with 5V external power supplied. In the depicted configuration, 5V is the selected input for the hex inverters, the 555 timer is driving the good hex inverter circuit, and the good hex inverter circuit is enabled. The bad hex inverter circuit is off.

Next the switching noise of the two hex circuits was compared. The data collection was done with a board provided by the University of Colorado – Boulder which will be referred to as the stock board. The stock board is similar to the designed board presented above, so it is not presented here. Using this board allows the analysis to be completed with a proven design and allows team members to compare results more easily. Although the data presented here does not come from the designed board, similar results were reproduced by the designed board during bring up.

Figures 5 and 6 compare the response of the power rail, the quiet high pin, on a rising edge. The voltage drop for the bad circuit is 800mV while the drop for the good circuit is 300mV. This represents a 60% reduction in noise. Figures 7 and 8 compare the falling edge the quiet high pin, showing the bad circuit has a 1,000mV spike in voltage while the good circuit has a 250mV spike. This represents a 75% reduction in switching noise. Figures 9 and 10 compare the response of the reference plane, the quiet low pin, on a rising edge. The bad circuit has a voltage spike of 500mV while the good circuit has a voltage spike of 100mV. This represents a decrease in switching noise of 80%. Finally, Figure 11 and Figure 12 compare the switching noise across the LED during a falling edge. The bad circuit has an excess voltage drop of 1.6V, while the good circuit has an excess voltage drop of 1.2V. This represents a decrease in switching noise of 25%.

Figure 5: The quiet high pin response (depicted in green) to a rising edge from the timer circuit (depicted in yellow) on the bad hex inverter circuit showing an initial voltage drop of approximately 800mV.

Figure 6 The quiet high pin response (depicted in green) to a rising edge from the timer circuit (depicted in yellow) on the good hex inverter circuit showing an initial voltage drop of approximately 300mV.

Figure 7: The quiet high pin response (depicted in green) to a falling edge from the timer circuit (depicted in yellow) on the bad hex inverter circuit showing an initial voltage rise of approximately 1V.

Figure 8: The quiet high pin response (depicted in green) to a falling edge from the timer circuit (depicted in yellow) on the good hex inverter circuit showing an initial voltage rise of approximately 250mV.

Figure 9: The rising response for the quiet low pin on the bad hex inverter circuit showing an initial voltage rise of approximately 500mV.

Figure 10: The rising response for the quiet low pin on the good hex inverter circuit showing an initial voltage rise of approximately 100mV.

Figure 11: The falling response for the LED pin on the bad hex inverter circuit showing an initial voltage drop of approximately 1.6V.

Figure 12: The falling response for the LED pin on the good hex inverter circuit showing an initial voltage drop of approximately 1.2V.

Lessons Learned

The results of the experiment show significant improvement in switching noise by following a few simple, free, best practices: place decoupling capacitors close to their IC, use a reference plane, and do not share returns. Failing to do this resulted in as much as five times more switching noise when compared to using best practices. Overall, this experiment was a success and provided strong evidence of the importance of using these best practices in board designs.

The designed board had one unexpected feature where the LEDs can be illuminated even if their hex inverter is disabled. This is due to the timer circuit being able to source some current to the LEDs. A better design, as shown by the stock board, is to power the hex inverters and use a switch on each timer circuit to enable the LED output. This requires fewer switches and avoids the erroneous dimly lit LEDs.

Additionally, the switch layout on the designed board is not intuitive. Although they are labeled appropriately, locating the switches near each other would have made the functionality of the board more intuitive. It was also redundant to have a toggle for the timer circuit and isolation switches for each hex circuit. Using the setup described above would have been simpler and required fewer parts.

Using solder pace sped up the assembly process and created clean joints; however, in the future, less solder paste can be used. Using too much allows the parts to slide and become crooked. Using less causes them to fall into place. Finally, starting with a large board size made the design process and assembly easier. In the future, sticking with a larger board size and then optimizing to make it smaller if needed will work well.

References

[1] Center, J. D. (2024 September). Timer Board. Jack’s Portfolio. https://www.jackdcenter.com/pcb-design/timer-board

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